1. Field of the Invention
This invention relates to an echo canceller for enabling full duplex digital data communication in a transmitter/receiver unit when connected via a hybrid circuit to one end of a two wire line.
More particularly this invention relates to such an echo canceller in which a memory unit is addressed by a sequence of data bits transmitted over a predetermined data interval, in which the memory unit contains a set of digital estimates of the near end echo of the data transmitted over said data interval, each digital estimate of the set corresponding to one of a number of sample periods per data bit period and one of the possible said sequences of data bits, in which once per sample period a said digital estimate is provided from the memory unit and is applied via a digital-to-analogue converter to an analogue summation circuit together with the received signal to suppress said near end echo in the received signal, and in which an error signal circuit derives from the output of the analogue summation circuit an error signal which is applied to the memory unit such that once per sample period an error adjusted digital estimate is written into the memory unit.
2. Description of Related Art
An echo canceller as described above is known from patent specification GB No. 2,007,946 B (see FIGS. 10 and 12). It is also known from the article by N. Holte and S. Stueflotten in IEEE Transactions on Communications, Vol. COM-29, No. 11, November 1981, pages 1573-1580. The Holte article denotes the principle used in this echo canceller as memory compensation in contrast with previously known echo cancellers using a digital transversal filter as a compensation circuit. Thus with memory compensation the data bit sequence is used to address a memory which stores the actual digital echo estimates, in contrast to transversal filter compensation where the signs of the data bit sequence determine addition or subtraction of coefficients stored by the filter so as to synthesise the digital echo estimates.
The Holte article describes an echo canceller which can be effective at a line data rate of 80 kbit/s for a line length of 7 km. The attenuation of the received signal at this frequency on this line length may be up to 30 db. The near end echo of the transmitted signal will be attenuated by the hybrid by at least 10 db. Thus to ensure a satisfactory 20 db signal-to-noise ratio for the received signal, the echo cancellation circuit is required to attenuate the near end echo in the signal received via the hybrid by 40 db. Holte indicates that at this frequency of 80 kbit/s, the echo impulse response of the line which must be covered to provide 40 db attenuation has a duration of 5 data bits, and proposes compensation of 8 samples per data bit period with a 12 bit word for each echo estimate. The size of the read/write RAM digital memory required to hold the echo estimates addressed by 5 data bits is thus 2.sup.5 .times. 8.times.12=3 kbits.
For an integrated services digital network (ISDN) a subscriber transmitter/receiver unit is now required which is capable of operating at a line data rate of 160 kbit/s. An article by R. P. Colbeck and P. B. Gillingham in IEEE Transactions on Circuits and Systems, Vol. CAS-33, No. 2, February 1986, pages 175-182 describes an integrated circuit transmitter/receiver unit with memory compensation echo cancellation capable of operating at 160 kbit/s line rate. This uses 14 bit words in the RAM memory, addressed by a 5 data bit history with 8 samples per baud. The memory size is thus 2.sup.5 .times.8.times.14=3.5 kbits. This is said to provide 45 db of echo cancellation which, with a hybrid echo attenuation of 10 db and a required signal to-noise-ratio for the received signal of 15 db, will accommodate a cable attenuation of the received signal of 40 db which covers an 80 kbit/s received signal over a line length of 5 km or a 160 kbit/s received signal over a line length of 4 km. Thus echo cancellation for the full range of subscriber line lengths up to 7 km at the required line data rate of 160 kbit/s is nowhere near achieved by the Colbeck design even for the signal-to-noise ratio of only 15 db. These subscriber transmitter/receiver units are required to be a high volume low cost item with the cost being largely determined by the chip area of the integrated circuit. FIG. 8 of the Colbeck article shows approximately one quarter of the chip area occupied by the memory. We consider that to achieve a desirable signal-to-noise ratio of 20 db for a line length of 7 km at 160 kbit/s line rate it is desirable to have at least a 9 bit data history. With the Colbeck design this would increase the memory area by 16 times and hence the total chip area by approximately 4 times, which is clearly unacceptable.
An article by T. Svensson in Ericsson Review No. ISDN, Vol 61, May 1984, describes an echo canceller for use at 160 kbit/s which is called a dual RAM filter. Thus memory compensation is effected by partitioning the RAM memory into two sections. The memory is addressed by a 7 bit data history with 3 bits being applied to the one partition and 4 bits being applied to the other partition. The outputs of the two RAMs are added before application to a digital-to-analogue converter. It is stated that the advantage of a dual RAM configuration compared with a single RAM configuration is that the total RAM size will be considerably smaller. The bit length of the words in the RAM and the number of samples per data bit period are not stated, but if they were 14 bits and 8 samples as in the above-discussed Colbeck article this would result in a memory size of (2.sup.3 +2.sup.4).times.8.times.14=2688 bits. The nature of the circuit used for adding the two RAM outputs is not stated. However, assuming that parallel buses are used, as shown by Holte and Colbeck, together with a parallel adder, this circuit for the addition will incur a chip area penalty to partly offset the reduction in memory area achieved by partitioning. Furthermore, as stated above, we consider that at least a 9 bit data history is desirable. With the Svensson design, two RAMs addressed respectively by 4 bits and 5 bits would double the memory size to approximately 5 kbits as well as having the area penalty of the circuit for addition, which is unacceptable. We have considered the possibility of extrapolating the Svensson design by further partitioning the memory to three partitions each addressed by three data bits. This would enable a 9 bit history to be accommodated by the same memory size as the dual partition memory disclosed by Svensson but would greatly increase the area penalty of the circuit for addition and so still be unacceptable.